r/chipdesign

Folks,

I'm building a team for a new compute chip that I want to tapeout. I have the architecture ready and validated(simulated), in talks with a few service partners for PD and post silicon. But the problem I'm facing is hiring for RTL talent. I need a core RTL team who has an implementation experience (not integration).

I've tried linkedin, job portals and agencies but the process is slow and not able to find anything solid.

If you guys can help me point to a place where I can reach RTL engineers, it'll be a big help.

FYI, We are a funded business, the path to tapeout is ready, partners are ready. I need a good team to speed up the execution. Any help is appreciated.

Thanks.

Like I got an entry level job offer from a company (that was a unicorn startup founded 7 years ago) that makes 1.4B revenue with 280 employees and the only thing they do is make a puzzle game. A single puzzle game. that equates to around 5M/employee in revenue and around 2.5-3M/employee in net profit.

In comparison, most chip design specifically fabless design houses are barely breaking even. Like in continental Europe I know a company that claims to be "the largest fab-independent European design group with world-class expertise in analog, digital, mixed-signal and high-voltage IC design" only makes around 20M revenue GROSS with around 120 employees. That's only 166k/employee and god knows how much profit they make per employee.

The sad part is I've spent around 2-3 years in total work ranging from RF/mmWave to Biomedical to SiPho and I always thought that I would earn more or possibly have the possibility to start my own startup.

Now, looking back the net salary they offer me AS AN ENTRY LEVEL(BSc) graduate is more than what I would earn as a manager or SM in Europe even in Apple Munich etc. and is comparable if not more than what an Apple entry level PhD grad makes after taxes and that is CA HCOL versus LCOL area. Why is chip design so horrifically bad of an industry? Like why do people continue choosing it when there are so many companies, and buyers squeeze companies against their own competition to crush any earnings potential.

And the moat of companies generally doesn't come from Hardware generally it seems like hardware is heavily commoditized. Even if you're SOTA a buyer will still pressure you against the competition. Say you have a PMIC chip with say 82% efficiency and you're closest competition has 77%. You can assume the same for PA's or integrated systems etc. you're literally fighting against each other where the upfront cost is insanely high and the marginal cost is low so they try to make you guys fight absolutely horrendously just to make horrifically bad margins.

Like even in SiPho there are tons and tons of players in CPO. SerDes the same, Biomedical AFE's tons of people. Like it's so horifically bad that you have no moat no matter how much you try. The only moat comes from audience lock in such as CUDA or ARM ISA's which are generally software related.

Automotive silicon design is entering a phase where functional safety, cybersecurity and artificial intelligence (AI) can no longer be treated as separate concerns. In connected, software-defined vehicles, safety outcomes depend not only on protection against random hardware faults, but also on resilience to malicious interference and software vulnerabilities. As a result, many of the decisions that determine system safety are now made at the silicon architecture level.

Read the full article by Enrique Martinez-Asensio, Functional Safety Manager at EnSilica…

https://www.edn.com/automotive-silicon-in-the-era-of-ai-functional-safety-and-cybersecurity/

Enrique Martinez-Asensio is functional safety manager at EnSilica. He has more than 35 years of experience in the semiconductor industry, having worked on mixed-signal IC design and technical support and management in several semiconductor companies.

Just joined as an intern at Intel in Physical Design, suggest topics and key concepts to brush up early to stay ahead of the curve and perform well

Hi, I'm hiring for Anthriq, an early-stage startup building custom silicon from scratch.

Small team with real ownership.

Open roles: RTL, Verification, Physical Design, Compiler/Toolchain, all senior, hands-on.

Looking for engineers who've been through a full chip cycle and want to do it again with full ownership from day one.

Apply here - anthriq.com/careers

I used to work in a large EDA company. I was wondering if anyone here has attempted to build EDA tools? If so what tool did you build and how hard was it? How long did it take?

I’m thinking about building a tool myself. Maybe open source it.

Need some genuine career advice from people in semiconductor packaging/SI-PI roles.

Right now I’m working in an OSAT-type environment where my role is kind of a mix of Advanced Package Design and SI/PI. Over the last few years I’ve worked on things like:
- Advanced package/RDL/substrate design
- High-speed routing
- SI/PI simulations and debugging
- UCIe/LPDDR/HBM related issues
- Package bring-up and coordination with different teams
- A bit of NPI exposure too

The problem is I’m now at a stage where I need to decide whether I want to go deeper into SI/PI specialization or move more toward package design + NPI/program side responsibilities.

I currently have two offers:

1. AMD
   - More SI/PI focused role
   - Feels more aligned with deep technical work in high-speed/package architecture
   - Slightly lower compensation

2. Broadcom
   - More package design + NPI focused
   - Better compensation
   - But honestly, a lot of what I read online talks about very long working hours and higher pressure/workload there

Long term I want to stay in advanced packaging/interconnect technologies and maybe eventually move into areas like heterogeneous integration, photonics integration, advanced architectures, etc.

I’m honestly confused about which direction is better for long-term growth.

A few things I’d really like input on:
- Is going deeper into SI/PI a better long-term specialization?
- Or does package design + NPI open broader opportunities later?
- Which path tends to have better stability and growth in the industry?
- How different are the cultures at AMD vs Broadcom in reality?
- If you were early/mid career in this field, which one would you pick and why?

Would really appreciate advice from people actually working in these areas instead of generic internet opinions.

For XNOR gate, I have these multiple different transistor-level implementations, which variant would you guys recommend and why ?

-> Figure 5 of https://eepower.com/technical-articles/cmos-implementation-of-xor-xnor-and-tg-gates/#

-> Figure 7.6 of https://www.researchgate.net/public...ATE_LOGIC_FOR_POWER_OPTIMIZATION/figures?lo=1

-> two different implementations in https://en.wikipedia.org/wiki/XNOR_gate#CMOS

-> Figure 1 till Figure 6 of [https://www.researchgate.net/publication/228447428\_A\_new\_design\_of\_XOR-XNOR\_gates\_for\_low\_power\_application](http://A new design of XOR-XNOR gates for low power application)

https://preview.redd.it/ia5goq02l12h1.png?width=1388&format=png&auto=webp&s=ed8829f0a2ad25a99bda7cbb305a55cbd0424cf9

https://preview.redd.it/tjnowd03l12h1.png?width=1978&format=png&auto=webp&s=1e18c1362ebfdeac2b2b6bda72c7e2d3ced8404e

https://preview.redd.it/hdaz42v3l12h1.png?width=976&format=png&auto=webp&s=79018537077bff6863075bbcc11e45a810c5ee35

https://preview.redd.it/up944iq4l12h1.png?width=1932&format=png&auto=webp&s=3e08d1db263f63d24528e739565f6c6aa6e77a8f

(Edit: schematic shown is a simplified version of Fig. 18 in this paper.)

Today I ran into the circuit below for biasing cascodes, which I never saw before. What would be the advantage(s) of generating the cascode bias voltages (Vcp, Vcn) in this way? (I mean, compared to classic approaches like the ones in this post)?

Since in the circuit below the generation is achieved through both NMOS and PMOS diodes, is it perhaps better across corners due to some weird NMOS/PMOS cancellation effect?

Thanks in advance for any ideas!

P.S. Or if anyone knows an early reference proposing this type of biasing, that would also be great!

https://preview.redd.it/juep41ac8y1h1.png?width=947&format=png&auto=webp&s=ba571bfc837af6eb39c72d346ba2c8ab0fe189bb

Hi, I’m a student looking into bottlenecks in EDA workflows. I’ve done a few small FPGA projects in both Quartus and Vivado, and even for small designs I found synthesis and place-and-route could easily take 10–15 minutes.

This year I also had the chance to tape out a small accelerator on a 40nm process through my university. In that flow, full PnR runs often had to be left overnight, which made me curious about what timelines look like in industry for larger and more complex designs.

For people working in ASIC or FPGA design professionally:

• How long do synthesis, placement, CTS, routing etc. typically take for your designs?
• Roughly how large are the blocks you work on (standard-cell count, macros, area, process node, etc.)?
• How much time is usually allocated for physical design within a project schedule?
• How many PnR iterations are typical before timing/power/area targets are met?
• Can you control the underlying placement/routing strategies and optimization algorithms or are the EDA tools fairly black box?

I’d be especially interested in hearing about experiences from modern advanced nodes as well as FPGA workflows at scale.

Anyone here interested in joining an FPGA Hackathon in Poland?

I’m looking for 1–2 teammates. If you have experience with FPGA development, embedded systems, digital design, or just want to build something cool, send me a DM to have a discussion.

I am started working 2 months ago I am new to analog layout design it self, my TL told to learn about AI and to implement it on daily bases but I am not clear on which AI is better and how I cn implement it on regular bases, I do normal chat gpt for certain topics but how to utilize in layout, if anyone know please help me out.

I have my python interview for RTL Design position at graphcore. Can someone please help me with the kind of questions they ask and what to focus on while preparing? TIA.

Update : I have 3+ yoe

Hi everyone,

I’m an Electronics and Communication Engineering student from India, and recently I’ve become very interested in Analog IC Design as a career. I’m trying to understand whether this field is truly the right fit for me before I commit deeply to it.

What attracts me is that analog design feels intellectually deep and less “replaceable” compared to some other tech fields. I enjoy electronics fundamentals more than pure coding. But at the same time, I keep hearing that analog IC design is extremely difficult, highly competitive, and takes years before someone becomes genuinely good at it.

So I wanted honest advice from people who are already in this industry or studying it seriously.

Here are my questions:

What does the day-to-day work of an analog IC designer actually look like?

Is it mostly simulations and debugging, or is there still creativity involved?

How mathematically intense is analog IC design in real jobs?

Do you constantly use advanced mathematics, or is strong intuition more important?

How hard is it for an average electronic student to enter this field?

I’m not from a top college, so I want realistic answers.

What skills matter the most for getting internships/jobs in analog IC design?

CMOS fundamentals?

Network theory?

Control systems?

Semiconductor physics?

Verilog/SystemVerilog?

SPICE simulations?

Layout knowledge?

What projects would genuinely impress recruiters?

I don’t want “resume filler” projects — I want projects that actually help me learn.

Is pursuing an M.Tech/MS almost necessary for analog roles?

Especially in India, can someone realistically enter analog design with only a B.Tech?

How important is coding in analog IC design careers?

Should I still focus heavily on programming/data structures, or should I spend more time strengthening core electronics?

What are the biggest misconceptions students have about analog IC design?

What part of this field usually makes people quit?

How is the work-life balance

With AI advancing rapidly, do you think analog IC design will remain a strong long-term career

If you could restart your journey as a student wanting to enter analog IC design, what would you do differently?

A little about me:

I genuinely enjoy electronics fundamentals.

I’m willing to study deeply, but I also don’t want to romanticize the field without understanding the reality.

I want a career where I can become highly skilled over time instead of doing repetitive work.

I’d really appreciate brutally honest advice, especially from people working in semiconductor companies or pursuing higher studies in analog/mixed-signal IC design.

Thanks in advance.

I wanted to know what kind of questions they ask, and more specifically, what coding questions they ask. Is it gonna be like python scripting, or just general programming that i can do with C?