r/chipdesign

Has anyone actually made money licensing silicon IP as a small team or solo? Curious about real stories

Not talking about ARM or Synopsys level companies — I mean regular engineers or small teams who designed an IP block and managed to license it out.

Always wondered if this is actually viable outside of big corporations. Like:

- How did you find buyers?

- Was it royalty-based, flat fee, or something else?

- Did you go through a marketplace or direct deals?

- How long before you saw real money?

Do RISC-V SoC startups actually need ready-made motor control IP, or do they just build it in-house?

Been reading about the RISC-V ecosystem growing fast especially in robotics and EV space. Curious about one thing — when a fabless startup is designing a motor control SoC, do they typically:

a) License a ready-made FOC (Field Oriented Control) IP block

b) Build it from scratch in-house

c) Hire a contractor to build it custom

Like is there even a real demand for synthesizable, bus-portable motor control IP from a third party? Or is this kind of IP so specific that companies always prefer to own it internally?

Also — would an FPGA IP marketplace (like OpenCores, or similar) even be a viable channel to reach these buyers, or is that too low-end for serious SoC work?

Just trying to understand how this space actually works. Appreciate any insight from people who've worked at fabless companies or RISC-V startups.

Hey folks,

So I recently got an offer from a startup(15 employees) that’s been founded by two ex-directors from a big analog & mixed-signal MNC. The cool part is that the company is purely analog-based, which feels kinda rare these days.

For context, I’m a recent master’s graduate from IIT Delhi and I’ve always been genuinely interested in analog design. I also have a small plan of possibly doing a phd later, though I’m not entirely sure about it yet. The not-so-cool part is that the pay is pretty low compared to what other established startups/MNCs are giving. That said, they told me I’ll actually get to work on real design and not just CAD grunt work.

Now I’m kinda torn and wanted to get some insights from people here:

1. Is it worth joining a startup like this for the experience even if the pay is low in the beginning?

2. What are the most important questions I should ask them before accepting? (like what blocks I’ll work on, tape-outs, etc.)

3. If I do join, what should I focus on learning in the first 1–2 years to build a strong profile (schematic, layout, simulations, verification, etc.)?

4. If I stay for 3–4 years and then move to another company in India (say TI/ADI), what kind of salary prospects can I realistically expect?

Anyone here who’s been through the startup → MNC path in analog design, I’d love to hear your insights.

Thanks in advance 🙏

Currently working in the defense industry doing PCB design and am absolutely bored out of my mind with how slow everything is, along with the mediocre pay. Looking at the potential salary of ASIC/VLSI design roles is really tempting me to go back to school. I graduated from an average state flagship with a 3.88 GPA and currently have 2 years of postgrad industry experience along with 10 months of internship experience. Haven't taken the GRE, but I have always done very well on standardized tests so I feel confident there.

Point is, I feel fairly confident I can get into a non-thesis masters programs at a good ECE school, but I was wondering which schools you guys feel would prepare me the best for industry. I did notice that many of these schools such as CMU serve as a pipeline to companies such as Apple and Nvidia, so that's something I'd like to consider as well.

Hey everyone,

I’m planning to learn RTL to GDS flow and found the NPTEL course by Prof. Sneh Saurabh (IIIT Delhi).

Has anyone taken it? How’s the teaching and depth? Is it beginner-friendly or more advanced?does it cover complete topic as required for interviews?

Would you recommend it for someone aiming for VLSI / Physical Design roles?

Also open to better or more hands-on alternatives if you have any suggestions.

Thanks!

As the title says, is anyone preparing for CDAC exam on april 12th for chip design, if yes please share your resources or pyq's etc.. anything on the exam.

I’m an RTL design engineer for a large semiconductor company, with about 5 yoe. From my observation RTL designers either choose to be architects or managers. Some may progress to become principal engineers. Personally I don’t really enjoy managerial work (assiging tasks, scheduling, meetings etc). Architecture work may sound interesting but I noticed it involved a lot of writing specs/documentation which is not as fun as actual implementation/debugging problems. The principal engineer route sounds good but I’m not sure if the salary is comparable to the other roles. Any senior engineer with experience in these roles can advise and maybe share how different is the job and pay between these 3 roles?

If I have Vdd=1.2V and 55nm process, and for the first stage (folded cascode) of a two-stage ota where I'm not too concerned with outupt swing, I have been sizing the current mirror devices such that they have ~150mV gate overdrive (Vgs-Vth=150mV and gm/id in the range of 10-12). Vdsat turns out to be slightly less than 150mV. I make sure that Vds is greater than Vdsat by 50mV at the DC operating point. The point to notice is Vdsat is bounded by gate overdrive.

Now with Vdd=0.72V and 22nm process, for the same task I don't have the luxury to choose such large gate overdrives. In fact, even for 5*Lmin the Vdsat is actually greater than gate overdrive when the overdrive is in the 70-120mV range.

To minimize relative current mismatch, large Vgs-Vt helps in strong inversion. But If I can't afford Vds (margin included) more than say 150mV, then Vdsat is 100mV. Vgs-Vth actually turns out to be ~70mV (gm/id value ~20).

What's wrong with my thought process?

I’m currently digging into a 22nm FD-SOI process and have a few questions regarding body biasing and device types. I'm trying to wrap my head around the practical implementation of Back-Gate (BG) biasing:

Figure from GLOBALFOUNDRIES webinar on YouTube

1. I’m curious about the limits of FBB in a standard regular vt fet (eg. NFET in P-well). Specifically, if I short the P-well and Deep N-well together to bias them positively, what are the primary risks compared to the Flipped Well (lvt fet) approach? Furthermore, I’ve seen designs where the back-gate is tied directly to the front-gate to create a 'stronger' switch. In a 22nm FD-SOI process, is this a problem for an rvt NFET when the switch is ON (VG​=VDD​)? Does the BOX provide enough isolation to prevent diode conduction from the P-well to the N+ source/drain, or is this technique strictly reserved for Flipped Well/LVT devices?"
2. 4-Terminal vs. Multi-Terminal Models: there are device models that expose only 4 terminals (G,D,S,B) and others that expose extra terminals for the Deep N-well and Substrate (eg. egslvtpfet in the figure below). When using the 4-terminal model, how are the DNW and Substrate connections handled? Do these terminals require explicit manual connections in the layout?

Figure from GLOBALFOUNDRIES webinar on YouTube

Would appreciate any insights from those who have experiences in 22FDX or similar nodes!

Has anyone here gone through a face-to-face interview for a Physical Design role at NVIDIA? I’d really appreciate it if you could share your experience especially around the interview format, types of questions asked, and what areas to focus on while preparing

Hello everyone.

I am a recent EE graduate and want to pursue a career in CMOS VLSI design. Unfortunately, I do not have relevant coursework from university, and my undergrad research focused on high-level design rather than the area I want to pursue.

I am an international student, and there are not many digital IC works done in my country. Most openings are in circuit design, PCB, testing, etc.

My long-term goal is to eventually land a strong position at a high-tech company. To get closer to the field and to enter the US ecosystem, I want to do a PhD first. I applied this cycle but have not received any acceptances, so I am treating it as a rejection and starting to improve myself for the next cycle.

Right now, I see two options:

1. Pursue a Master’s degree in chip design (probably in Europe)
2. Work in industry in my country, the work may not be directly related to the area I ultimately want

People around me (who have only worked in industry) keep telling me that academia does not really teach you how to do things in the real world, and that a Master’s would just delay my life by two more years.

What makes me hesitate is that this industry experience would likely be mostly irrelevant to both the PhD programs I want to apply to and the work I eventually want to do.

I honestly do not have enough experience to judge which path is better, and I do not want to regret my choice later. I would genuinely appreciate any suggestions or ideas from people who have faced or witnessed a similar situation.

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