u/kunalg123

A lot of students ask the same VLSI career questions:

What should I learn first?
Is physical design better or RTL design?
Do open-source EDA tools really help?
How important is RISC-V?
Can students build real chip-design projects without expensive tools?
What skills are actually useful for semiconductor jobs in India?

I tried to answer these in detail in this podcast conversation, along with my experience building open-source chip design programs and working with students across VLSI, RISC-V, FPGA, and semiconductor training.

Full podcast:
https://youtu.be/Av_LxKNrqV8

Would be happy to hear thoughts from students, freshers, and working professionals in this community.

VSDSquadron FPGA Trainer Kit for High School Chip Design is now ready to ship — a complete hands-on platform to learn RISC-V, FPGA, and real chip design from school level.

Been in this space for a while and something has always bothered me.

Most people I know who work with FPGAs - including myself for a long time - treat it as a black box. You write HDL, synthesize, place and route, deploy. You understand the timing constraints, the resource utilization, the tool flow.

But ask what a switchbox actually does, or how a LUT is physically constructed, or how the connection fabric routes signals between CLBs - and most people either go quiet or give a textbook one-liner.

I came across a workshop recently that specifically addresses this. Not an FPGA programming course. It teaches you to design the internal fabric itself in Verilog. LUTs, CLBs, switchboxes, connection boxes - you build them from scratch and simulate a working mini-FPGA architecture.

Here is what a participant built and published from a previous cohort:

github.com/ShonTaware/FPGA_Design_Fabric_Architecture

I genuinely could not find another course that goes this deep into FPGA internals. New cohort starts 18th May, registration closes in 10 days.

Workshop link: https://www.vlsisystemdesign.com/fpga/

Curious whether others have found resources that go this deep - or whether most people just accept the black box and move on.

If you’re trying to understand how a chip is actually designed end-to-end, this flow gives a clear picture.

From System Design → RTL → Synthesis → Physical Design → Signoff,
each stage has its own set of tools and learning curve.

For many students and professionals, the real challenge is not theory —
it’s getting structured, hands-on exposure across this full flow.

What’s encouraging today is that there are accessible ways to start exploring these stages step-by-step,
build small designs, and gradually move toward more advanced implementations.

That’s exactly the approach VLSI System Design (VSD) has been focusing on - helping learners move from concepts → labs → real design workflows.

If you’re looking to get started or go deeper with guided learning and hands-on labs, you can explore here:
https://www.vlsisystemdesign.com/vsd_products/

The goal is simple:
make it easier to learn by doing, at your own pace, with the right structure.

A hiring manager at a top semiconductor company told me this last week. I wasn't surprised.

India wants to train 1,000,000 chip engineers by 2030. Lam Research is building virtual fabs. The Tata Dholera fab hits First Silicon in December 2026.

But here's the quiet revolution nobody is talking about:

The chip design interview changed.

Recruiters at Qualcomm, Intel, and NVIDIA don't just read your resume anymore. They open a browser. They go to github.com/[your name]. They look for:

→ Did you do RTL-to-GDSII on a real design?

→ Can I see your physical design layout?

→ Did you actually tape out anything?

A student from a tier-3 college in India recently joined a top VLSI company. No IIT. No internship at a big firm. Just a public GitHub repo with a complete RISC-V SoC flow using open-source SKY130 PDK.

That repo was his resume.

At VLSI System Design (VSD), we built our entire philosophy around this: "Learning by doing" → GitHub → Job.

From RTL design to tapeout. From a ₹2000 VSDSquadron board to a public chip layout. No expensive cleanroom. No ₹50,000 EDA license. Just open-source tools, real projects, and a GitHub link.

The 1 million chip engineers India needs by 2030 won't be built in classrooms. They'll be built commit by commit.

Is your GitHub your resume yet?

👇 Drop your GitHub link below. Let's see what India's chip engineers are building.

In 2020, a student from a tier-3 college in Andhra Pradesh sent me a message.

"Sir, is chip design only for IIT students?"

I did not reply immediately. I wanted to think about whether I was going to tell him the comfortable thing or the true thing.

The true thing is this: chip design jobs in India have historically gone to people from a handful of colleges. Not because tier-3 students are less capable. Because the tools, the real flows, the hands-on experience — they never reached those colleges. The knowledge was locked inside companies and elite institutions.

That student joined a 10-day RISC-V workshop. Open-source tools. Real processor design.

He is now at a semiconductor company in Hyderabad.

I am not sharing this to congratulate anyone. I am sharing it because that question — "is this only for IIT students?" — is sitting silently in the minds of lakhs of ECE graduates right now.

And most of them have already accepted the answer as yes.

It is not yes.

Tata is building a fab. Micron is here. CG Power signed. The India Semiconductor Mission is not a press release anymore — it is concrete and steel going into the ground. The demand for chip design engineers over the next five years is unlike anything this country has ever seen.

The engineers to fill those roles do not exist yet in sufficient numbers. That is not a problem. That is a window.

But windows close.

Every VSD program opens for registration this May — 10-day intensives, 3-month programs, K-12 tracks, real hardware, real tapeout. If you want to see what this looks like before committing, there is a free live roadshow on April 30th.

This is not a course listing. This is the door that student from Andhra Pradesh walked through.

https://www.vlsisystemdesign.com/vsd_products/

Tag the ECE graduate in your life who quietly stopped believing this industry was for them.