u/Lazy-Astronomer8932

Hi, I’m a student looking into bottlenecks in EDA workflows. I’ve done a few small FPGA projects in both Quartus and Vivado, and even for small designs I found synthesis and place-and-route could easily take 10–15 minutes.

This year I also had the chance to tape out a small accelerator on a 40nm process through my university. In that flow, full PnR runs often had to be left overnight, which made me curious about what timelines look like in industry for larger and more complex designs.

For people working in ASIC or FPGA design professionally:

• How long do synthesis, placement, CTS, routing etc. typically take for your designs?
• Roughly how large are the blocks you work on (standard-cell count, macros, area, process node, etc.)?
• How much time is usually allocated for physical design within a project schedule?
• How many PnR iterations are typical before timing/power/area targets are met?
• Can you control the underlying placement/routing strategies and optimization algorithms or are the EDA tools fairly black box?

I’d be especially interested in hearing about experiences from modern advanced nodes as well as FPGA workflows at scale.