r/FPGA

So I've been working on this design for the past six or seven years, and almost 10 years total in FPGAs, and somehow I still ran into something today that I'd never hit before. Figured it's kind of funny in hindsight and worth posting as a case study.

Our design has a lot of clock domains and we're constantly passing signals across them, single bit, multi bit, counters, the whole mix. We try to do things the right way: flip flops where appropriate, double flip flops for single bit synchronizers, handshakes for multi bit, and grey code for counters. Standard stuff.

Today something was glitching out and it was screaming "CDC problem" at me. We had a counter, we were converting it to grey code, and passing it across the domain. On paper, all good.

What I was missing: this counter wasn't running freely up to saturation and rolling over. It was getting reset back to zero somewhere in the middle of its range.

And that's the gotcha. Grey code only works for CDC because consecutive values differ by exactly one bit, so if the receiving domain samples during a transition it either latches the old value or the new value, never garbage. That assumption only holds when the counter increments by one. If you're sitting at 5 (0111 in grey) and you reset to 0 (0000), you've got three bits changing at the "same" time, and the receiver can sample any of the intermediate states.

Grey code on a counter is only safe if the counter is free running or only ever increments by one. The moment something can yank it back to zero, or jump it by more than one step, you've broken the invariant that makes grey code work, and you're right back to the multi-bit CDC problem you thought you'd solved.

The fix in my case was just adding a handshake on the CDC after the grey coding, which works. Though honestly at that point the grey code isn't really doing anything for you anymore, the handshake is what's making it safe. But I left it in because it's not hurting.

Moral of the story is more the gotcha than the fix. Anyone else been burned by this one?

This recent vivado licence change has just ruined my plans. I ordered a kria kr260 from abroad yesterday, which is supported in free tier Vivado license. However due to the new restrictions on free tier license, I can't stop wondering that if it is waste of money to buy vivado compatible FPGA boards if the user intends to develop on free tier?

My only experience is limited to archaic altera board and I was hoping for transferring that knowledge to vivado ecosystem. But due to this recent development it turns out I need to target an alternative ecosystem, which one do you recommend? Lattice or any other?

Thanks a lot .

I have the following code block, but I am not sure if I should use value <= 0 or value <='0. What is the difference between the two?

logic [31:0] value, tap;    

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    value <= '0; // or value <= 0; ?
  end else begin
    vlaue <= value + tap;
  end
end

We are a electronics company looking for an experienced PCB designer for a compact, high frequency RF board.

The project involves:

• Multi-channel RF front-end using analog devices transceivers

• Artix-7 FPGA as the digital backend

• Controlled impedance, mixed-signal, multi-layer stackup

• L-band operation

What we need:

• Schematic design and PCB layout (we will provide the reference design and component selection)

• Stackup design with proper RF/digital isolation

• BGA fanout for both the FPGA and RF transceivers

• SI/PI analysis

• Gerber and fabrication-ready outputs

Must-haves:

• Prior experience with RF SDR based board layout

• FPGA BGA fanout experience (Xilinx 7-series or equivalent)

• Familiarity with high frequency PCB materials and controlled impedance design

• Altium or Cadence Allegro

Nice-to-haves:

• Experience with SDR platforms (PlutoSDR, FMCOMMS, USRP, etc.)

This is a paid engagement with potential for ongoing work across multiple board variants. Please share relevant portfolio work when reaching out.

DM or comment if interested.

Hello dear FPGA'ers

I am currently frustrated and I need help.

I have created a custom AXI4 MM slave IP in vivado/VHDL and connected to the MPSoC through axi smc.

Now I want to use a PS DMA to read data from the DDR and transfer this data to my IP.

But the resources on the web are just overwhelming.

Below is my block diagram.

I am using Vitis for the software and my PS is an R5 and I am using FreeRTOS for that.

I have already tried with direct CPU writes and checked the ILA and it worked (I saw my data on the ila lines)

Now I'd like to move further so that my CPU can focus on other tasks while the DMA is doing the work in the background.

How do I configure this PS DMA?

Help.

Thanks

https://preview.redd.it/229nvnoo722h1.png?width=1252&format=png&auto=webp&s=50f6f6c0b9818bf34061562a010644f28994d3b6

I’m planning to buy an development board specifically for RISC-V development using chipyard.

The VC707 and VCU118 are overpriced and total overkill for my budget, while the Arty A7 has way too few LUTs to run anything complex (like BOOM setups).

What is the actual "sweet spot" board right now?

Hello everyone, For decades, the computing industry has been locked into the binary paradigm. While silicon scaling is hitting its physical limits, most optimization efforts remain at the software level, leaving the underlying foundational logic untouched. I have developed and officially registered the NDR-Octabit-Core, a computational logic system designed to run on a native Base-8 architecture instead of traditional Base-2.

⚙️ The Core Innovation The NDR-Octabit-Core bypasses the standard binary tree-structures for data processing. By implementing a native 8-state logical mapping, the system achieves a predictable O(1) time complexity in execution benchmarks, eliminating the latency fluctuations (O(log n)) typical of traditional binary address and allocation mechanisms. Scientific Timestamp & Registry: The architecture, formal benchmarks, and Core implementation in C++ have been published and indexed via Zenodo with a public Digital Object Identifier (DOI): https://doi.org/10.5281/zenodo.20128879

🚀 The Next Frontier: Scaling into Quantum & Hardware The mathematical framework of the NDR-Octabit-Core naturally aligns with the next generation of computing: Hardware (FPGA/ASIC): Moving from software emulation to native multi-level logic gates (similar to advanced MLC/QLC concepts but at a logic-gate level). Quantum Computing (Qudits): Traditional quantum computing focuses on 2-level qubits. The NDR-Octabit logic is structurally ready to map natively into 8-level Qudits (Octits), potentially offering a more efficient control layer and real-time state tracking without classical binary translation overhead.

💼 What I am looking for: The foundational logic is proven and benchmarked. I am now looking to transition this project from a validated scientific model into a physical/emulated reality. I am seeking: Deep Tech Investors / Venture Capital: Interested in pre-seed infrastructure, semiconductor licensing, or paradigm-shifting hardware patents. Hardware & FPGA Engineers: To collaborate on building a hardware description layer (VHDL/Verilog) for physical prototyping. Quantum Computing Labs/Researchers: To co-develop the driver layer, mapping the Base-8 NDR logic into multi-level quantum simulators (like Qiskit) or physical qudit platforms. If you are tired of incremental software patches and want to discuss a foundational architecture shift, let's connect. Contact: jarav2001 [at] gmail.com

Obviously if you've got IPs or you need the modularity ( calling the same module multiple times). Otherwise isn't just dumping everything in 1 file just easier and better ? Design wise, it is easy to access intern registers, the TB stays the same. You also save a bunch of registers you save.

Anyone here interested in joining an FPGA Hackathon in Poland?

I’m looking for 1–2 teammates. If you have experience with FPGA development, embedded systems, digital design, or just want to build something cool, send me a DM to have a discussion.

How can I configurated the signals of FFT provided by IP Core on ISE Design Suite ? I need to implement the FFT on Basys 2 FPGA board for read a current wave and verify if happens a electrical fault in the system

Hi all,

A few weeks ago, I started an HFT project based on FPGAs.

The goal is parse market data (NASDAQ ITCH protocol) and to do some book keeping on the market state. The project is surprisingly "not that hard" (not trivial but not impossible) if you know your way around FPGAs.

Right now, the project is "just" a book keeper. I plan on implementing better memory management (which is the hard part of this project), corrupt data recovery and finally a basic strategy able to execute orders so I can start loosing money at lightning speeds :D

And yes, I do know that not many firms are into FPGAs as it's pretty niche and not many strategies require such speeds etc... But still, I think it's interesting !

I made some technical blog posts (currently 6 parts) : https://0bab1.github.io/BRH/posts/Trademaxxer_MoldUDP64/

If you are not into hardware design but still wanna learn about FPGAs in HFT + some basic technical background... Or just have a good time, you can find a much more simple (entertainment oriented) project overview on YouTube : https://www.youtube.com/watch?v=ogaTn6oB-TQ

Don't hesitate if you have any question !

NOTA : I hope this does not come out as shameless self promotion, it kinda is when I think about it but it's more of a way for me to share the "soft-hardware" aspect to the HFT community. I usually hang out in r/FPGA where people sometimes talk about HFT so I though it would be relevant.