r/FPGA

Hey guys, I am a graduating electronic engineering student, expected to graduate in June 26. I'm considering applying for a New Grad FPGA Engineer at one of the big trading firm like Jane Street, HRT, 2Sigma, Optivier. If anyone can tell me their experiences about applying at these types of companies that would be really helpful. Honestly I can't say I have too much experience about playing with actual board, I've always stopped before burning that onto the boards. I've done some FPGA projects using Vitis HLS and system verilog, but they're mostly about AI inferencing accelerators, which are quite far away from their low-latency applications ... Are there any suggestions for me?

Hey all im in my second to last year and im 0-5 with interviews for internships. I am incredibly depressed and feel like giving up. Ive never met anyone in my school that has this problem. Usually once people get an interview they land it. Is this normal? Or am i just a wierdo?

Hello everyone,

My colleagues and I created a high-resolution digital measurement system using a Cyclone V FPGA [1, 2]. The device has hybrid time-to-digital converter (TDC) / binary digital storage oscilloscope (DSO) functionality, and I developed and patented it during my physics PhD research in order to precisely study ultrafast signals at low cost.

Others have contacted me saying that they found the publication useful (it contains many low-level FPGA details), so I wanted to share it here. Moreover, I'm developing a PCB version (FPGA + SMA connectors etc. in a handheld form factor) as a replacement for existing time-taggers / digital oscilloscopes. My question to this community is:

Would you potentially be interested in purchasing such a device?

The goal is to significantly reduce cost compared to leading time-taggers / oscilloscopes while offering similar capabilities. I'm in talks with a leading metrology lab for independent certification, but would not go through all the trouble if only I would end up using it. So, let me know if you might be interested in a digital measurement device with the specs below, printed in the next 6-12 months (16-level analog bandwidth is possible but would likely double the price and development time).

Happy to answer any questions, and thank you for any feedback!

- Dr. Noeloikeau Charlot

Spec sheet (TBD):

Target Price: $250 - $750

Architecture: FPGA carry-chain

Digital Resolution (Bin Size): 5 - 15 ps

RMS Jitter (Single-Shot Precision): 1 - 30 ps RMS

Number of Channels: 1 - 8 channels

Dead Time (Min Inter-Event): 5 ps - 1.5 ns

Readout Rate (Data Transfer): ~3 Gbit/s

Memory / Buffer Size: 1024 Kbit + ~1 GB DDR

Input Bandwidth (Max Input Freq): 200 MHz

Edge Capture Per Channel: Simultaneous rise & fall

Trigger / Threshold: Fixed comparator

Input Impedance: 50 Ohm (SMA)

Host Interface: USB 3.0

Form Factor: Thumbstick

Software Ecosystem: Python

References:

[1]: https://ieeexplore.ieee.org/document/9585689

[2]: https://patents.google.com/patent/US20260023145A1

I am currently an EE undergrad who is focusing on Digital Signal Processing / Control Theory coursework. Unfortunately, my program offerings is very limited in that theres only 1 FPGA course offered (theres no other workarounds. I CANNOT take CE/CS courses due to lack of offering). I have some prior background programming mcu's and general PC applications,

I'm very aware that FPGAs are a somewhat blank slate in which you can program in practically any digital circuits you want. I've been just taking all the digital design courses.

Hi everyone,

I’m planning my thesis in the VLSI domain, focusing on ASIC design and IP core development, and I’m looking for some guidance.

Could you suggest:

- Good thesis topics that are both practical and industry-relevant?

- Recommended tools/flows (open-source or commercial) for ASIC/IP design?

- Any useful resources or projects to get started?

Thanks in advance for your help!

Hi, I'm trying to implement a 100x100 sub-frame median filter, which is used to reduce salt and pepper noise from a 3124x3030 input image data. Any idea on how to compare the 10000 pixel data to arrange them in ascending order. This median operation needs to be applied on all the pixels, so how to efficiently design the filter in my FPGA design?

Hello!

Does anyone have experience with onsite interviews at Altera?
I'm specifically interviewing for Product Engineer. Any tips/tricks/advice in general or specific to Product Engineering would be greatly appreciated!

It's my first ever onsite interview so I'm pretty anxious about it.

Thanks in advance!

ok i dont understand something, this has happened twice to me, i do some project on vivado, i get results, i take screenshots, and when i open the same project that i saved days ago, somehow the post implementation timing fails and i start getting negative slack and idk what hapoens. i cant seem to solve this issue and i feel like i am like dreaming of the timing stuff being correct the last time i checked. why is my vivado gaslighting me?