u/Just-End6752

I have the following code block, but I am not sure if I should use value <= 0 or value <='0. What is the difference between the two?

logic [31:0] value, tap;    

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    value <= '0; // or value <= 0; ?
  end else begin
    vlaue <= value + tap;
  end
end

In SystemVerilog, we can use for loop directly inside a module and it is synthesizable. It can also scale the code well. For best practice, do we still need generate block in such a case? What is the advantage to use generate block?

Let's say I declare a variable as logic [3:0] val. All the following expressions work, but which one is a better (or best) practice?

val = val + 5;
val = val + 4'd5;
val = val + 'd5;
val = val + 'b0101;
val = val + 'b101;
val = val + 4'b101;

Since EDA playground couldn't synthesize SystemVerilog codes. I used Vivado synthesis tool to run my codes. I used systemVerilog (always_ff, for loop, logic key word etc) as my design language, and synthesis is successful.

However, when I go to project settings, I only have two choices for the target language: Verilog/VHDL. The default in my case is Verilog.

So, there is a conflict here regarding the HDL language used. I picked up systemVerilog when this file was created, but the target language in the settings section has to be Verilog.

Any comments on this HDL usuage discrepancy for the same project?

I can simulate SystemVerilog codes using different simulators provided by EDA playground, but no way to synthesize SystemVerilog features, e.g. logic keyword etc.

Am I making a mistake here?

I am trying to learn to build up a simple test bench for an adder using system Verilog. The interface signals are all fine, but I got all zeros in / outside the adder. Here is the code output:

inside the adder: a(0) + b(0) = sum(0)
Generating class signals: a = 19, b = 182, sum = 0
a =          19, b =         182, sum =           0

Here is the code:

class transaction;
  randc int a;
  randc int b; 
  logic clk;
  int sum = 0; 
  constraint c1 {a inside {3, 7, [11:20]};}
  constraint c2 {b inside {1, 7, [10:255]};} 
  function void display();
    $display("Generating class signals: a = %0d, b = %0d, sum = %0d", a, b, sum);
  endfunction
endclass

interface vif();
  int a, b; 
  logic clk; 
  int sum; 
endinterface

module adder(input int a, b, input clk, output int sum);
  initial begin
    begin
      sum = a + b;
      $display("inside the adder: a(%0d) + b(%0d) = sum(%0d)", a, b, sum);
    end
  end
endmodule

module test; 
  logic clk;
  
  transaction trans;
  vif vif_if();
  
  initial begin
        trans = new();
        trans.randomize();
        trans.display();
  end
  
  initial begin
    vif_if.clk = 0;
    forever #5 vif_if.clk = ~vif_if.clk;
  end
  
  initial begin
  vif_if.a = trans.a;
    vif_if.b = trans.b;
//    vif_if.sum = trans.sum;
    $display("a = %d, b = %d, sum = %d", vif_if.a,vif_if.b, vif_if.sum);
    vif_if.clk = trans.clk;
  end
   
 adder uut(.a(vif_if.a), .b(vif_if.b), .sum(vif_if.sum), .clk(vif_if.clk));
   
 initial #50 $finish;
  
endmodule

When we call randomize() function, pre_randomize() will be called first, then randomize(), and finally post_randomize() as shown in the following code. However, when it executes, only post_randomize() is called. Does anybody know why?

class randclass;
  rand  bit[1:0] p1;
  randc bit[1:0] p2;
  bit[1:0] parity;
  
 // function void pre_randomization();
  function void pre_randomize();
    parity = 0;
    $display("pre_randomizatoin()");
  endfunction
  
  function void post_randomize();
    parity = p1 ^ p2;
    $display("post_randomizatoin()");
  endfunction
endclass

class randwrap;
  rand int prw;
  rand randclass c1;
  function new();
    c1 = new();
  endfunction
endclass

module test;
  randclass myrand = new();
  randwrap mywrap = new();
  int ok;

  initial begin
    ok = myrand.randomize();
    if (!ok)
      $display ("myrand randomize failure");
  end
endmodule 

I got the error which says p1 & p2 are not declared as shown in the following code, but both are declared in the class declaration. Can somebody tell where the problem is?

class randclass;
  rand  bit[1:0] p1;
  randc bit[1:0] p2;
  bit[1:0] s1, s2;
endclass
module test;
  randclass myrand = new();
  int ok, state;  
  initial begin
    myrand.rand_mode(0);
    $display("1st: p1 = %0d, p2 = %0d", p1, p2);
    myrand.p2.rand_mode(1);
    $display("2nd: p1 = %0d, p2 = %0d", p1, p2);   
    state = myrand.p2.rand_mode();
    $display("3rd: p1 = %0d, p2 = %0d, state = %0d", p1, p2, state);
    ok = myrand.randomize();
    state = myrand.s1.rand_mode();
    $display("4th: p1 = %0d, p2 = %0d, state = %0d", p1, p2, state);
  end
endmodule

I got the following compilation error message:

ERROR VCP2000 "Syntax error. Unexpected token: [." "testbench.sv" 14 11

Here is the code:

function int sum_array(int array[5]);
    int sum = 0;
    foreach(array[i])
        sum +=array[i];
    return sum;
endfunction
module test;
    bit [7:0] array[3:0];
    // genvar i;
    int i;
    for (i = 0; i < 4; i++) begin
        line 14: array[i] = $random; // initialize array with random value
    end
    foreach(array[i]) begin
        $display("array[%0d] = %0h", i, array[i]);
    end
    $display("sum = %0d", sum_array(array));
endmodule

Different simulators gave out different error messages. However, the above error message was cited in all situations. This is also the only error message given by Aldec Riviera Pro 2025.o4 simulator, even if I used "int i" instead of "genvar i".

I am still new to System Verilog. Can somebody help me figure out this "interface left open" error:

"vif"
The port 'vif' of top-level module 'test' whose type is interface 'dut_if'
is left unconnected. It is illegal to leave the interface ports unconnected.
Please make sure that all the interface ports are connected.

The following is the code:

interface dut_if(input logic clk);

logic [7:0] data;

logic valid;

logic ready;

// Clocking block for the testbench (Driver/Monitor)

default clocking cb @(posedge clk);

default input #1step output #2ns;

output data, valid;

input ready;

endclocking

// Modport to restrict the testbench to using the clocking block

modport TB (clocking cb);

endinterface

module test(dut_if.TB vif);

initial begin

// Synchronize to the clocking event

@(vif.cb);

// Drive signals through the clocking block

vif.cb.data <= 8'hA5;

vif.cb.valid <= 1;

// Wait for 2 clock cycles using the cycle delay operator

##2;

// Sample a signal

if (vif.cb.ready)

$display("DUT is ready at time %t", $time);

vif.cb.valid <= 0;

end

initial #50 $finish;

initial begin

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule

I tried to test the usage of some functions in system Verilog. However, I kept getting errors as below:

1. When I used "f" directly in both prototyping and function call, I got the following error message:

Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 19: token is ';'
f;

2. When I used "f()", the error message was as follows:

Error-[URMI] Unresolved modules
testbench.sv, 19
"f ();"
Module definition of above instance is not found in the design.

What should be the correct way to test the function in the following code block?

task t;

#1 $display("@ %0t ns, Task End", $time);

endtask

function void f;

fork

$display(" %0t ns, calling task from function", $time);

t;

join_none

$display("@ %0t ns Function Exit", $time);

endfunction

module testbench;

f;

endmodule

I have the following code on EDA Playground, but it couldn't compile.

module top_module ();

class packet #(pw = 8, dest = 32, pri = 5, type dtype = bit);

dtype [pw-1:0] payload;

bit [dest-1:0] destionation;

bit [pri-1:0] my_priority;

endclasss

packet pkt1 = new();

packet #(16, 64, 3, logic) pkt2 = new();

packet #(, , , bit[3:0]) pkt3 = new();

packet #(16, 128) pkt4 = new();

endmodule

The error I got is:

Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 8: token is 'packet'
packet pkt1 = new();
^

Any advice here on how to make this code work?

The following code should print out the display method in the child class since it has a virtual key word in the parent class display(). However, I got a printout "display: parent!" as the output (run in hdlbits). Does anybody know why? Or, maybe it is a tool issue?

module top_module ();

class parent;

function new();

$display("parent class!");

endfunction

virtual function void display();

$display("display: parent!");

endfunction

endclass

class child extends parent;

function new();

$display("child class!");

endfunction

virtual function void display();

$display("display: child!");

endfunction

endclass

initial begin

parent p;

child c;

p = c;

p.display();

end

initial #10 $finish;

endmodule