Made a timing constraint library — every file has the formula and theory, not just the values
Tired of finding .xdc files with no comments and no explanation of why the numbers are what they are. Built this to fix that.
58 constraint files across 13 boards (Basys3 to Alveo U50 to Tang Nano 9K). Covers SPI, UART, DDR3, HDMI, RGMII, MIPI CSI-2, AXI4, I2S. Each file has the datasheet formula and what to actually change for your device. (all consolidated)
Also threw in an AI that takes your Verilog and generates the XDC(mostly trash as of now honestly) , and a timing calculator if you want to punch in your own datasheet values.
CI validates every PR so the files don't rot.
https://github.com/devtyagi3909/constraintforge
live(website)- https://devtyagi3909.github.io/constraintforge/index.html
still missing a lot of boards. PRs are welcome. What interfaces do you wish were documented better?
help me make this a better pr from it is as of now,
again, all and every PR is WELCOMED