Does verilator , find combinational loops , i mean i tried it on a .sv file and it finds them through UNOPTFLAT but when i try to run it on bigger files I doesn't catch them any suggestions.
+ I need to force include a .vh verilog header file, how to do it?
Suggest me lectures that i should watch for IC designs could be NTPEL, PAID COURSE , or any lectures from bigs unis
I have to work on the linting process.
I have 3 files top.v submodule.v and .vh file which is a library header and contains all defines .
And this .vh is placed in a different folder.
There is a Make file , that calls the .pl file to generate .v files and 1 make file calls the verilator and lints the .v
The issue I am facing is that the verilator couldn't find my .vh file although i have mentioned in my assets.vc(which contains all the paths).
As a result i have to use all the DEFINE inside assets.vc and that works which I don't want to do any solutions to it.
Second is if I write the entire path of top.v and submodule.v it works if i give relative path with -y it becomes unable how to solve it.
So i am an Electrical undergrad and I got a chance to be an intern in a pcie start up company on the second day they put me on linting and debugging codes I don't know what to do. No much senior help they said reverse engineer
I have basic understanding in verilog systemverilog and digital electronics. What to do?