
▲ 122 r/chipdesign
First silicon errata today: didn't connect power
This is what being an idiot look like, let this be a cautionary tale.
Here is the long version : https://talesonthewire.com/thoughts/broken_doc/ but you can still shame me in the comments for not having run LVS without reading it.
u/Ill_Huckleberry_2079 — 3 days ago