u/HenryKissingerJr

Hey everyone,

I’m looking for someone experienced in RTL/Verilog who can help me build:

1.UART Controller

2.RISC-V Core (single-cycle or pipelined)

I’m already comfortable with Verilog and the prerequisites, and I can do this myself — but lately I’ve been feeling a bit drowned and low on motivation.

I learn best through interaction and discussion, so I’m looking for someone who can:

Guide me through the design

Help me think through things when I get stuck,

Collaborate rather than just give solutions

I’m on a **tight timeline**, so this is a bit urgent.

This is **paid**, happy to discuss based on your experience.

If you’ve worked on UART/RISC-V or similar RTL projects, please DM or comment. I’d really appreciate the help.

Thanks!