u/FutureAd1004

I’m currently digging into a 22nm FD-SOI process and have a few questions regarding body biasing and device types. I'm trying to wrap my head around the practical implementation of Back-Gate (BG) biasing:

Figure from GLOBALFOUNDRIES webinar on YouTube

1. I’m curious about the limits of FBB in a standard regular vt fet (eg. NFET in P-well). Specifically, if I short the P-well and Deep N-well together to bias them positively, what are the primary risks compared to the Flipped Well (lvt fet) approach? Furthermore, I’ve seen designs where the back-gate is tied directly to the front-gate to create a 'stronger' switch. In a 22nm FD-SOI process, is this a problem for an rvt NFET when the switch is ON (VG​=VDD​)? Does the BOX provide enough isolation to prevent diode conduction from the P-well to the N+ source/drain, or is this technique strictly reserved for Flipped Well/LVT devices?"
2. 4-Terminal vs. Multi-Terminal Models: there are device models that expose only 4 terminals (G,D,S,B) and others that expose extra terminals for the Deep N-well and Substrate (eg. egslvtpfet in the figure below). When using the 4-terminal model, how are the DNW and Substrate connections handled? Do these terminals require explicit manual connections in the layout?

Figure from GLOBALFOUNDRIES webinar on YouTube

Would appreciate any insights from those who have experiences in 22FDX or similar nodes!