Hi all,
I’ve been working as an analog designer for ~5 years and have taped out a few chips. One thing that still surprises me is how manual the early design phase still is.
Even for fairly standard blocks (OTA, bandgap, LDO, etc.), we still:
- Pick an architecture largely from experience
- Manually build schematics connection by connection
- Iterate through SPICE simulations
- Spend days or weeks tuning device sizes to meet specs
What’s interesting is that a lot of these designs are variations of known topologies, yet the workflow hasn’t changed much.
A large part of the effort feels repetitive—especially the initial architecture selection and device sizing loop.
I’ve been thinking about whether parts of this process—especially at the schematic level—can be partially automated, not to replace designers, but to speed up early-stage exploration.
Curious how others here think about this:
- How much of your schematic-level work feels automatable in practice?
- Where do you think automation would break down?
- Would you trust a generated starting point if it passed basic simulations?
- Is the real bottleneck architecture selection, or sizing/optimization?
My intuition is that even partial automation could significantly reduce design iteration time, but I’m curious where experienced designers think the limits are.