Cross-validation question for glass-substrate folks: BEM vs Palace FEM spread on TGV impedance (also discussed in r/chipdesign)
Hi r/Semiconductors,
I posted this in r/chipdesign earlier today and a couple of people there suggested also bringing it here for industry perspective: https://www.reddit.com/r/chipdesign/comments/1ta9mg2/
Short technical version (skip the rest if you already saw the chipdesign thread):
I cross-validated a multiconductor BEM solver against three independent solvers - FastHenry2, OpenEMS, and Palace FEM - on glass-substrate through-glass-via (TGV) impedance. The geometry-disjoint test corpus is 78,840 unseen geometries drawn from a 6.75M-row BEM dataset.
The number I'd genuinely love this community's perspective on: BEM vs Palace FEM frequency-spread envelope sits at 6.73% median from 28-200 GHz on glass-TGV geometries.
For those of you doing HBM4 / chiplet-package / glass-interposer signoff work in industry: is 6.73% within tolerance for the kind of signoff envelope your team uses? Tighter? Looser? Curious whether this matches what you see when you cross-check your own setups.
A related sub-question: the coaxial approximation built into most EDA tools comes out wrong by 55-225% on glass in my testing (vs full-wave). Does that match industry experience or is my characterization of "current EDA glass support" too pessimistic?
Methodology, repro scripts, full corpus, and audit gates are documented at chipletos.com/why-glass for anyone who wants to dig in. Happy to drop into the chipdesign thread or answer here.
Not trying to sell anything - genuinely looking for industry sanity-check on the freq-spread envelope before I run a wet-lab VNA campaign on it.