u/2082_falgun_21

Image 1 — Can I name states arbitrarily?
Image 2 — Can I name states arbitrarily?
▲ 4 r/FPGA

Can I name states arbitrarily?

I am wondering if I can name states arbitrarily given that I properly design the controller state table according to it?

u/2082_falgun_21 — 1 hour ago

I have a doubt about datapath designing

  1. Why is there 0 in front of x and y registers? 0:x and 0:y i mean I understnad for d 9 came from the finite state machine present right before.
  2. I do not understand the role that multiplexer is playing. Based on the figure right after
  3. I know digital logic's multiplexer though. It is used to select one input.
u/2082_falgun_21 — 14 hours ago
▲ 13 r/pens

Uniball Signo Retractable Gel Pen UMN 155N (0.5mm) original refill writing dry. What can be done to fix this?

If possible. I love the design of this pen and stuffs. But its refill are always like that. And that I hate. Its new pen batch is not like that but refills are always like that. That is the reason why I have been using disposable UB-150 micro rollerball pens from uniball.

If you guys have fix for this, I could make use of the refill I have had. Gemini is saying to burn it in lighter for a second. I do not want to try what bots say.

u/2082_falgun_21 — 17 hours ago
▲ 2 r/ECE

Timing diagram of Serial In Serial Out Shift Register. After which clock pulse do I get data in Q2,Q1,Q0?

The input was 011.

I do not see the proper output in this timing diagram. It is showing everything as zero. It would take 6 clock pulse for the total output to be available. But this timing diagram just continues 0 till 6 clock pulse.

u/2082_falgun_21 — 4 days ago