▲ 10 r/RISCV
sse2rvv: An MMX/SSE/AES-NI C Intrinsics to RVV C Intrinsics Translator
github.comu/omasanori — 8 hours ago
u/omasanori
▲ 14 r/RISCV
Ventus: A RISC-V-based GPGPU Research Project
A Spike-based simulator and a Clang-based OpenCL toolchain for Ventus are available. According to the toolchain README, Ventus is a RV32IMAZfinxZve32f with modifications to vector instruction set to support SIMT-style warp units.
u/omasanori — 2 days ago
▲ 19 r/RISCV
Server Platform Spec Ratification ETA End of May
The RISC-V Server Platform and Server Platform Test specifications define the basis of common requirements for servers.
- The RVA23 profile defines ISA requirements for application processors.
- The Server SOC specification depends on RVA23 and defines non-ISA requirements for server-grade SoCs like interrupt controllers, PCIe, etc.
- The Server Platform specification depends on the Server SOC specification and defines requirements for server hardware and software components other than SoC like bootloader interfaces.
The Server Platform Test specification defines the procedures of compliance test and such.
u/omasanori — 2 days ago
SiFive Has Raised $400M Round, Semidynamics Invested from SK Hynix, Codasip's Pivot to CHERI Cybersecurity Processor IP
eetimes.comu/omasanori — 2 days ago
▲ 24 r/RISCV
RISC-V 101 – what is it and what does it mean for Canonical?
ubuntu.comu/omasanori — 3 days ago
▲ 10 r/RISCV
Specification Inception for Large Integer Arithmetic Extension Proposed by DAMO Academy (Alibaba)
It is a regular (non-fast-track) ISA specification proposal under Security Horizontal Committee and (unsurprisingly) there are no specification document yet.
Large integer arithmetic is also known as arbitrary-precision integer arithmetic. Making it faster benefits cryptography applications and mathematical computation.
u/omasanori — 4 days ago