u/immortal_sniper1

Here is some context before i ask my question:

I will have to design a GPS time synchronisation system for a project. I have 2 option :

1. squeeze the GPS module on the main PCB and find space on the back panel for a SMA or something small enough for GPS antenna that goes outside. In this case i will have a precise clock source on the PCB and GPS PPS will come with a direct trace from the module to my FPGA. (might need to use a resistor divider to reduce signal voltage, not sure yet if HP or HD banks are needed) in this case i can say i have more or less datasheet PPS accuracy

2. have the GPS module on another board connected to my main FPGA board with some cable , might be able to negotiate RJ45 for twisted pair cables. Problem in this case is that now PPS signal will travel a lot longer and through cable and potentially pick up tons of noise and also get attenuated. Thing is I hate the idea of wiring something directly in a FPGA , also after a long cable i am not so sure how the signal will attenuate and potentially DC shift.

In this case what type of buffer should i use? Or should i try a differential receiver driver like RS485 or LVDS? I am a bit afraid that anything on the PPS line would severely reduce performance.

Personally i would go for 1) but the decision is not entirely mine and if it is decided to go with 2) what would be a good way to reduce the effects of the long cable (5-10m).

PS since this is early in the project expected performance was not decided but i guessing at least +-1us.

Any thought or advice how to deal with situation/ have some better arguments then what i presented.

So is it possible to have on 1 panel multiple PCB projects?

As in in a normal panel i have NxM of the same PCB from the altium project.

I want to have x from project_A ; y from project_B ; z from project_C .

Why? it is a small PCB and they are mostly iterations of mostly the same stuff and i want to order them at the same time and also save some costs and time with assembly ( a lot of shared stuff between all of the projects.

IF it is possible then how?

I am designing a system and I need a lot of USB 2 ports with a lot of throughput. I have a few USB 3 available and i was considering useing something like the TUSB8044A https://www.ti.com/lit/ds/symlink/tusb8044a.pdf?ts=1777252391016&ref_url=http%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftusb8044a

So here is What I am not sure:

1. USB 3 Should be 4800 Mb/s but does this include or not the 480 Mb/s from the USB 2 that is in the same cable interface? like it is 480+4800 Mb/s effective? or USB 2 stops after it figured out it is talking with a USB 3 HUB?

2. Since the mentioned hub has Multi transaction translator (MTT) does this mean it can saturate all 4 downstream ports at the same time? ( provided the upstream port can handle my data) like a Ethernet switch that is from 1Gb to 4-8 100Mb ports ( this type of behaviour)

3. If i use 2 such HUBs cascaded to obtain & USB2 ports then all should still be at max speed , right?

4. after i cascaded 2 HUBs will the last 4 Ports have more latency or delay then the first 3?

Asking since i plan to use them for Video and audio and i am afraid it will de sync over time.

5. IF my most upstream port is a FPGA i get the USB3 from GTH/GTY transceivers, do i also need an ULPI for USB 2 ?