At what point in the design process should you be thinking seriously about signal integrity and is the schematic stage already too late
Doing more high speed design work lately and trying to figure out where signal integrity analysis actually fits in the workflow. I know a lot of si work happens at layout with field solvers and post layout simulation but i'm wondering how much can and should be caught at the schematic stage before you've committed to a physical implementation
Specifically thinking about things like impedance path planning, differential pair handling, memory bus topology. Feels like decisions made at schematic stage constrain what's possible at layout in ways that aren't always obvious until you're already there
how do people with more si experience think about this? is there meaningful si work you can do at schematic stage or is it mostly a layout and post layout activity?