u/No_Experience_2282

Hey guys,

I’ve recently began to wrap up development of my most recent CPU core, Anvil-Pro. While this has mostly been an educational endeavor, I’ve ended up with what may be a fairly solid FPGA softcore. Through development, I’ve attempted not just to “implement” but also, within reason, to “perform”. As such, the microarchitecture and decisions underlining it have been made with the explicit goal of high IPC/LUT.

My rationale was, worst case scenario, I learn strong fundamentals and end up with a resume item. Best case scenario, I may create something that could carve out a legitimate use case (however marginal) within the spectrum of demand.

Since, ultimately, the project is educational, I’ve chosen to make every decision top down from principle rather than from textbook or convention. This comes with the caveat that, ultimately, I will make suboptimal and poor decisions. I’ve implemented or reinvented many standard internal CPU structures, but have combined them in a way that is less commonly done. Importantly, the overall architecture was from what I reasoned to be effective, rather than from a model CPU.

This design philosophy has pros and cons. As to the cons, I am ignoring the previously discovered wisdom of everyone prior to me. I am also putting into practice something untested rather than proven optimal. As to the pros, I am creating something slightly interesting and perhaps less treaded. I also get to learn stronger architectural principles from the additional accountability.

Given all this, I hope to have established that Anvil-Pro is somewhat different from other softcores. While this difference is marginal, it is still worth noting. A question in my mind now remains: “Is this actually any good?”.

This is the reason for this post. If anyone is interested and has sufficient time to waste, could you evaluate my microarchitecture and tell me how it compares to convention inside its own performance class. Is my performance good, poor, decent? Are my decisions justified, is my architecture sane? I’ve yet to have someone actually look at this other than myself. To be completely honest I really don’t know, if i could do it all over again, what I would change.

If interested, there’s an architecture.md document detailing design philosophy. There are also several diagrams I’ve put together to illustrate my thoughts. You may also look through the verilog, but I would recommend against it. My coding style is rather convoluted in all honesty, especially given that this was built solo rather than as part of a team.

Please let me know thoughts and critiques, of which I’m happy to hear.

https://github.com/JohnH2448/Anvil-Pro

Note: I have not run timing analysis or FPGA resource usage estimates. I certainly plan to, but at this point I have not yet gotten to it. This is a first functional prototype.

A while back, I shared my first RISC-V core here: this is its architectural evolution and natural progression. It’s not fully “production-ready” yet, but I wanted to post it in case others find it interesting.

The CLINT and CSR paths are functioning quite well. While they still need deeper verification, they’ve reached a point where I’m comfortable presenting them publicly. There’s no RISCOF pass yet, but I expect it would largely succeed.

The design incorporates some non-traditional techniques, notably utilizing a ROB to enable a limited form of out-of-order behavior (without the usual complexity).

I’d appreciate any thoughts, feedback, or especially criticisms where they’re warranted.

Check it out here:

https://github.com/JohnH2448/Anvil-Pro