Is "execution model" a property of each abstraction level independently, or a top-level design principle?
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Hi everyone, I'm an Italian student following the awesome Onur Mutlu's Digital Design and Computer Architecture course (ETH/CMU 447, publicly available on YouTube). I'm trying to understand what "execution model" actually means — apologies in advance, English is not my first language and I used AI assistance to help me formulate this question clearly, but the confusion is genuinely mine.
The way it's introduced in the course, "execution model" sounds like a top-level design principle — you choose an execution model (Von Neumann, dataflow) and then derive an ISA and a microarchitecture from it. But in practice, both the ISA and the microarchitecture seem to have their own execution model independently — and they can differ. OOO processors are the obvious example: sequential at the ISA level, dataflow-like at the microarchitecture level.
This makes me wonder: is "execution model" just a per-level descriptor — a way to characterize how instructions fire at each layer of the hierarchy — rather than a single overarching principle?
The reason I'm confused is that Von Neumann is presented as an execution model, but it's much more than a firing mechanism — it also includes stored program and a specific hardware organization. Dataflow, by contrast, is described almost purely as a firing mechanism. So either "execution model" means different things in the two cases, or Von Neumann is being used as a shorthand for something more specific.
Is there a clean definition of "execution model" in the literature, or is it consistently informal?
IMHO the "problem" Is that pedagogically speaking the von Neumann model Is presented as an indivisibile package, but, since its introduction, a lot of abstractions were introduced, complicating the picture.
Thanks in advance.