u/Large-Raisin-5912

Image 1 — 20M Haircare query, never used conditioner in my life. Hair is dry and frizzy af
Image 2 — 20M Haircare query, never used conditioner in my life. Hair is dry and frizzy af
Image 3 — 20M Haircare query, never used conditioner in my life. Hair is dry and frizzy af
Image 4 — 20M Haircare query, never used conditioner in my life. Hair is dry and frizzy af

20M Haircare query, never used conditioner in my life. Hair is dry and frizzy af

Curly, dry, frizzy. Been using only shampoo my entire life and nothing else. Zero conditioner, zero mask, zero anything.

Just started looking into curl care and I'm lost. Open to both combo kits and individual product recommendations, available in India. Price is not a concern.

(attaching photos so you can see the damage yourself)

u/Large-Raisin-5912 — 3 days ago

Built RV32IM variants across single-cycle, pipelined, superpipelined, superscalar and OoO on actual simulation with CoreMark + custom micro-kernels covering low-high ILP, ALU-heavy to mem-heavy and ctrl-stressed patterns

Pipelined gains in order:

  • Early branch resolution EX→ID: +8.6%
  • 2-bit saturating predictor: +6.5%
  • BTB: +3.5%
  • Generalised MEM-to-EX load forwarding: +2%

CPI 1.31→1.06, CoreMark/MHz 2.57→3.17, within 2.3% of an unoptimised dual-issue superscalar

Same load-forwarding fix that gave +2% on the pipeline gave +17% on the superscalar; a load-RAW stall in dual-issue removes 2 slots per cycle, hazard handling becomes a cross-cycle dual-slot matrix problem

Once both were optimised the 2.3% gap became 46.8%

For more details: link

Toolchain: Verilator, Surfer, Ripes, GCC/LLVM, Spike/QEMU, RISCOF

u/Large-Raisin-5912 — 24 days ago
▲ 2 r/ASIC

Built RV32IM variants across single-cycle, pipelined, superpipelined, superscalar and OoO on actual simulation with CoreMark + custom micro-kernels covering low-high ILP, ALU-heavy to mem-heavy and ctrl-stressed patterns

Pipelined gains in order:

  • Early branch resolution EX→ID: +8.6%
  • 2-bit saturating predictor: +6.5%
  • BTB: +3.5%
  • Generalised MEM-to-EX load forwarding: +2%

CPI 1.31→1.06, CoreMark/MHz 2.57→3.17, within 2.3% of an unoptimised dual-issue superscalar

Same load-forwarding fix that gave +2% on the pipeline gave +17% on the superscalar; a load-RAW stall in dual-issue removes 2 slots per cycle, hazard handling becomes a cross-cycle dual-slot matrix problem

Once both were optimised the 2.3% gap became 46.8%

For more details: link

Toolchain: Verilator, Surfer, Ripes, GCC/LLVM, Spike/QEMU, RISCOF

u/Large-Raisin-5912 — 24 days ago