I have this rather complex board that already has an FPGA and esp32c3 mini module and also a big PMIC. There will also be an ESP32P4 as applications processor on it. The core rail of the esp32p4 usually is handled by a separate DCDC with the feedback pin partially controlled by the chip itself so that it has adjustable core voltage I think 1.1-1.3V. Espressif is also quite direct about using an dcdc converter from a short list they made. But I wonder, is it possible to just feed it from a fixed 1.2 or 1.3v rail? I don't need efficiency as the board burns a ton of heat already. The PMIC also has dynamic voltage scaling just not via analog feedback control but via I2C so it could do it in theory. I've already asked on the Espressif forum but no answer. Does anyone know if this can work? If it does it would be a much cleaner solution for me than adding another dcdc converter.
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So I am designing an FPGA containing board in KiCad 7 and have this issue where due to tight spaces and usually low impedance required apart from fanout I need to neck down a lot of traces. Already done, everything fits. Not just that but also when I switch layers the trace thickness changes to keep the right impedance. So I have routings with at least 1 often 2 trace width changes. When I try to length match that the entire track kinds gets highlighted as one net but only one segment with boundaries where the thickness changes gets the length detected and can be tuned. That's also the only part that has the gray outline of the min spacing shown. I could just adjust the target by subtracting the pieces not detected but there has to be a better way. The transition is good and overlaps I've tried pretty much everything but issue remains. Even happens when the width change is at a via and also even happens when I've checked that there's no stubs. Is this just a KiCad 7 thing, a general issue or am I doing something wrong?
I have this application where i have a digital board with a high power FPGA that draws up to 20a on it's 0.85v supply rail and overall the whole board about 2a on the 12v input and I need to connect it to a custom ADC board. The interface is LVDS. There are two ADCs both 40msps one 14b 4 channel the other 20b single channel. My plan was to just do AC coupled LVDS and some common mode filters but there's still the issue of the injecting noise through ground. The connector is as far away from the DCDC but still that's just 8cm on this compact board. I've looked into isolated LVDS but it's very expensive with that many lanes. How can this be done? I can't just route over a ground split even if the ground split is at the coupling capacitors right? That would feel very wrong in a way. Or can I? What are my options? I really need some decent noise on that ADC below far 1mv like 10uV RMS in the relevant frequency band would be nice. Coupling caps on the digital board or on the ADC board? I'm kinda lost here on what to do
So I have this design where i need a 0.85v 20a DCDC power supply down from 12v. External fet controlled by a PMIC, 1MHz nominal switching frequency, fast transients, low ripple all that, if you'd have guessed it's for an FPGA.
Currently I have input side the smaller caps front side forming a tight loop with caps on the high side fet 12v to ground and low side fet gnd to 12v. Plus 3 larger caps for bulk front side on each fet and mirrored on the backside. On the output side I also once again have most smaller caps front side with large bulk caps on the backside and set back towards the fets so underneath the inductor.
I've done some digging and TI tested backside placements with negative results where frontside performed best always. However they tested all or nothing, either everything front side, all input caps and IC back side inductor front side or only IC backside. I wasn't actually that surprised that it didn't perform. IC and inductor were on opposite sides with vias connecting them and all high frequency components had to go through the vias.
So now I wonder, are backside caps generally a poor choice or is it a good design to keep high frequency caps front side with tight loops and larger caps partially backside if it allows for a smaller loop area. My logic is the larger caps will have the highest currents in the loop but at the lowest frequency but that's still 1mhz. So what do you think yay or nay? Does anyone have personal experience with it maybe even done some emi measurements? Also TI only looked at input and output voltage ripple so injected EMI. I wonder if radiated EMI shows a different story.