u/Good_Layer_4623

Is Jain food/no onion-garlic based veg food served or possible to get in Qualcomm Bangalore office canteen lunch?

I am being considered for a Senior ASIC / RTL Design Engineer role in Qualcomm India. My background is: PhD, MTech and BTech in EE/ECE from an IIT Around 1 year of postdoctoral research experience Research experience in DSP/VLSI, algorithm-to-architecture mapping, RTL design, ASIC/FPGA-oriented implementation, low-power/high-speed design concepts Publications/patents in signal processing/VLSI-related areas Academic/postdoc experience, but no long full-time industry experience yet The role is broadly related to wireless/DSP IP design, microarchitecture, RTL coding, front-end ASIC design, synthesis/STA awareness, lint/CDC, and low-power/high-speed design. I wanted to understand the current realistic compensation range in India for someone with this profile. Specifically: What CTC range should I expect for a Senior ASIC Design Engineer / Senior Engineer-level role at Qualcomm India? How is the CTC usually split between base salary, bonus, RSUs, joining bonus, and other benefits? Does a PhD + postdoc usually help in negotiation, or is it mostly treated similar to a fresh PhD entry? Is there a meaningful difference between Senior Engineer, Staff Engineer, and Senior Staff Engineer levels for PhD candidates in Qualcomm India? What range would be reasonable to negotiate for in 2025–2026 market conditions?