Question about capacitor bank bus voltage deviations
I was wondering if anyone here has a general rule of thumb they follow for placing capacitors on a bus in an area that needs voltage support. I looked this up and found a guide from MISO where they recommend allowing no more than a 3% deviation per capacitor stage on a bus pre-contingency and no more than a 5% deviation per capacitor stage on a bus post-contingency. I'm curious to see what others have come across.
Thanks in advance!