Hey everyone,
I’m a solo developer working nights with zero budget on a new CPU architecture called Project RJ8A. I wanted to share a major milestone and get some feedback from the veterans here.
The Milestone: I just successfully generated the Verilog RTL for my proof-gated execution path and ran it through my master test suite. As you can see in the first screenshot, it passed 55/55 algorithms flawlessly (including Quicksort, Ackermann, and Hanoi).
In our current benchmark suite, the architecture shows a ~6.1x wall-time efficiency advantage compared to heavily optimized x86 (-O3 -march=native with guarding), assuming a 2 GHz Fmax target for the final ASIC.
The "Good" Problem (Screenshot 2): Up until now, I used an ECP5-85F for my hardware proofs. However, the full Sidecar-Wrapper design just exploded past the chip's limits. Yosys native 64-bit synthesis completed successfully (peaking at 52GB RAM usage on my workstation), but the design requires ~142,000 LUTs (169% utilization on the ECP5).
The Pivot: I'm currently migrating the entire pipeline to the open-source F4PGA toolchain targeting a Xilinx Artix-7 (A200T) / Kintex-7 to accommodate the massive routing graph. VPR is running right now.
Since I'm bootstrapping this entirely alone and don't currently have the budget for a high-end physical Xilinx dev board to flash the final bitstream, I'm relying heavily on strict toolchain verification (Yosys -> VPR -> STA).
Are there any F4PGA/VPR veterans here who have pushed >140k LUT designs through the open-source Xilinx flow? Any pitfalls regarding memory limits or routing congestion I should watch out for during the 12-hour PnR runs?
Also open to any academic/seed partners who want to collaborate on the first physical boot. Thanks for reading!
