This is my second PCB..the board dimensions are 60x35mm. MCU is a ESP32-C3 with u.FL connector, so no on-board antenna, hence no keepout zone .. I looked at all kinds of esp32 devkit pcb references i could find and also learned from a course that taught how to do a custom esp32 devkit. I have two 5V sources (both diode-ORed with SS14 Schottky diodes to prevent backfeeding), one coming from an external board that will provide power for the C3 (via an LDO) and the other is 5V from usb-c (which i will use to flash and debug).
My questions (beside did i get anything wrong) are
- i have a 10uF cap at the LDO 3v3 out, should I also put a 10uF at the 3v3 pad of the esp32 or is the 100nF enough?
- Is the way i did the USB-C connector through the ESD to the C3 fine? I connected the two 5VUSB1 pads with vias under the D+ and D- which seemed to be a standard way to do (at least i saw it in all 2 layer references) and didn't worry too much about perfect differential pairs because it seems to not matter too much at these speeds.
- I have two voltage-sense traces coming from the external board into esp32 ADC pins. One senses the remote supply node, and the other senses the remote ground node. I named the remote-ground sense net DGND_SENSE in the schematic and connected it to local GND through a net-tie so the sense return is distinct in layout while still referencing board ground electrically. Does that make sense, or should I just name that sense trace GND and avoid the net-tie? i am kinda leaning towards renaming and avoiding the net-tie.
- in my last pcb i did a via fence around the perimeter of the board. i'm not sure it is needed here as well.
- there is some empty space in the top right. i wasn't sure if i should "cut" that part off and have a non-rectangular shape or just not have any copper there or not worry about it and, keep it and use the space for a graphic on the silk screen layer. my understanding is the empty space will probably not harm, but if there's good reasons to cut it off i'd do that (e.g. if that reduces cost).
- trace width: it's a bit all over the place right now. i use wider power traces where possible and reduce where needed. i2c at 0.25mm .. D+ and D- 0.2626mm, boot and rst an 0.2mm .. i think i will make all signal traces 0.25mm unless less or more is better
Any feedback is very much appreciated!
edit: unfortunately my images were downsampled by reddit, i did upload much higher quality
u/Dayowe — 10 days ago