u/Boring_Ratio_4119

Image 1 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 2 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 3 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 4 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 5 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 6 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 7 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 8 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 9 — Review Request: Controllable Feedback/Feedforward Loop Board
Image 10 — Review Request: Controllable Feedback/Feedforward Loop Board

Review Request: Controllable Feedback/Feedforward Loop Board

Hi everyone, I posted here a while ago to receive reviews for my schematic, and I’ve finally completed my layout. Here is a brief overview of my project. I’m implementing a programmable feedback and feedforward control loop that takes in a 0.3V to +0.3V signal and amplifies it to 15V, while performing stability control within the STMG4 MCU.

Here are some of the current functionalities

  • Voltage shifter at the input stage of the PGA and ADC, shifting the input to a common mode voltage of 1.65V.
  • Two different amplifiers are connected in a summing amplifier topology, which adds the feedforward and feedback paths (FB_OUT and FF_OUT). 
  • Other common microcontroller peripherals (NRST button, crystal oscillator, USB, LDO, decoupling capacitors for supplies,. etc).

I’m using a Signal - GND - GND - Signal stackup, while routing my power (5V, 18V, +18V, and 3V3) on the top and bottom signal layers. While adding stitching vias to stitch the ground planes together.

However, I have identified some concerns in my current design. 

  • One of my op amps does not have a solid ground below (two vias interrupting the solid ground plane)
  • I’ve chosen my ADC input resistor value based on the DS12288 manual, which shows the maximum resistance for a given sampling rate. I also added another capacitor to the ADC input stage for compensation.
  • I’m worried that some of the power traces aren't thick enough, and I'm considering dedicating power layers (switching to a 6-layer stack-up).

 

Any feedback and responses to this design are welcome!

u/Boring_Ratio_4119 — 6 days ago