u/BigDeckSheep

Hi everyone, I am designing a compact, high-performance 3-phase motor driver for a robotics project. It uses FOC and is designed to handle high current peaks (approx. 40-60A).

Key Specifications:

MCU: STM32G474RE.

Power Stage: 6x N-Channel MOSFETs HYG011N04LS1TA driven by DRV8301DCAR.

Sensing: 2 Low-side shunt resistors for phases current sensing.

Interfaces: CAN-OPEN CiA402,Modbus RTU RS485, and USB-C for configuration.

PCB: 2-layer board 1oz copper thickness.

Specific concerns I’d like feedback on:

Gate Drive Loops: I’ve tried to keep the Gate-Source return paths as short as possible. Do you see any areas where parasitic inductance might cause ringing or EMI issues?

Grounding Strategy: I have implemented a split ground strategy (PGND for power, AGND/GND for logic) connected at a single net tie by 0R 0805 resistor. Is the placement of this connection optimal for this topology?

DC-Link & Decoupling Strategy: I am looking for guidance on sizing and placing the capacitors for the inverter stage:

Bulk Capacitance: For a peak current of 40A-60A and a PWM frequency of 25-30kHz, what is the recommended methodology to calculate the total bulk capacitance? I want to ensure the voltage ripple stays below 5% and the capacitors can handle the RMS ripple current without overheating.

Local Decoupling: At each half-bridge, I’ve placed a mix of 100nF and 1uF MLCCs. Is there a rule of thumb for the ratio between different capacitor values to suppress high-frequency switching spikes effectively? How do you determine the optimal quantity of these local caps based on the PCB's parasitic inductance?

Regen Chopper (Braking Circuit) Implementation: I am implementing a Regen Chopper using a single Low-side MOSFET to switch an external braking resistor, rather than a full Half-bridge.

Any kind of feedback is welcome. Thank you very much!