Going to the PLD dark side
I wanted to experiment with the zeropage. Devices at $7F80? Easy with 74HC30 and 74HC138. Devices at $0000? Hmm, that's a lot of OR gates. Writable interrupt vectors? Hmm.
This actually compiles! I'm excited! But 22v10s are sadly still in the mail. I should probably sleep anyway. 😄
Name decoder ;PartNo 00 ;Date 05/14/26 ;Revision 01 ;Designer koushiniku ;Company None ;Assembly None ;Location None ;Device g22v10 ;
/* inputs */pin 1 = CLK;pin 2 = R;pin [17..13,11..3] = [A15..A2];
/* outputs */pin 18 = !VIA_CS;pin 19 = !ACIA_CS;pin 20 = !RAM_CE;pin 21 = !ROM_CE;pin 22 = !OE;pin 23 = !WE;
/* address field */field address = [A15..A2];
/* definitions */WE = CLK & !R;OE = CLK & R;VIA_CS = address:[0000..000F];ACIA_CS = address:[0010..0013];VECTORS = address:[FFF8..FFFF];ROM_CE = address:[C000..FFFF] & !VECTORS;RAM_CE = !ROM_CE & !ACIA_CS & !VIA_CS;