u/Accomplished-Stay441

Custom RF Protocol (FS1000A/MX-FS-05V) - Losing sync on long payloads. How do you handle continuous clock recovery?

I’m working on an project where I’m trying to build my own custom RF packet framing from scratch. I am not looking to use established libraries like VirtualWire or RadioHead...I know they would solve this instantly, but my goal is to understand how low-level RF synchronization and protocol design actually work under the hood.

Hardware:

  • 2x Arduino Nanos (ATmega328P)
  • FS1000A (TX) and MX-FS-05V (RX) 315MHz modules

The Goal: I’m transmitting a custom frame structured as: PREAMBLE -> SYNC WORD -> LENGTH -> DATA -> CHECKSUM.

The Issue: My code works perfectly for very short payloads (like "AB" or "HI" even "abcdefghijklmno"). However, when I try to send a longer string (like "abcdefghijklmnopqrstuvwxyz" or a short sentence), the payload gets corrupted and fails the checksum.

My Current Approach: Currently, my receiver does a single timing alignment right after detecting the preamble/sync word: delayMicroseconds(BIT_DELAY / 2); After that, it enters a loop and samples continuously using a fixed bit delay (delayMicroseconds(416) for a ~2400 baud rate).

CODE: TX RX CODE

What I suspect is happening: I believe I am falling on clock drift. Because my TX and RX Arduinos have independent internal clocks, and I’m relying on a fixed delayMicroseconds in software, microscopic timing discrepancies are accumulating. By the time it reads the 30th or 40th bit, the receiver is no longer sampling in the center of the bit and reads garbage. I lack continuous bit synchronization.

Any insights, codes, help, pseudocode, or resources on how to implement would be massively appreciated. Thanks!

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▲ 2 r/DSP+1 crossposts

ETSI TS 102 361-1 BPTC(196,96): Is I(k) notation an ARRAY INDEX or POLYNOMIAL DEGREE?

Implementing BPTC(196,96) encoder per ETSI TS 102 361-1 (DMR standard).

I'm confused about the fundamental meaning of the I(k) notation in Figure B.1.

https://preview.redd.it/hdmpqu8kum0h1.png?width=1204&format=png&auto=webp&s=721f6deeefe8a21661f654c0b9b4c4c4891b99d5

Lets consider this:

Given 96 information bits: 1010101010....(96 bits total)

When ETSI Figure B.1 shows the data matrix layout with I(95), I(94), ..., I(0),

should I interpret this as:

INTERPRETATION A: ARRAY INDEX (Sequential Bit Position)

- The first bit (1) in my stream = I(0) = 1st bit position

- The second bit (0) = I(1) = 2nd bit position

- The last bit = I(95) = 96th bit position

- Naturally, bits arrive as: [I(0), I(1), I(2), ..., I(95)]

- To match Figure B.1 (which shows I(95) first): REVERSE with fliplr()

- My current code does this

INTERPRETATION B: POLYNOMIAL DEGREE (MSB-First)

- The first bit (1) in my stream = I(95) = coefficient of x^95 (MSB)

- The second bit (0) = I(94) = coefficient of x^94

- The last bit = I(0) = coefficient of x^0 (LSB)

- Bits naturally arrive as: [I(95), I(94), ..., I(0)] (MSB-first order)

- Figure B.1 shows this natural order; NO reversal needed

- fliplr() should NOT be used

- M(x) = I(95)·x^95 + I(94)·x^94 + ... + I(0) (message polynomial)

THE PRACTICAL QUESTION:

For my specific 96-bit stream [1,0,1,0,1,0,...]:

Should I do:

A) data_matrix = reshape(fliplr(data), 11, 9)' ← INDEX view

B)...data_matrix = reshape(data, 11, 9)' ← DEGREE view

What does I(k) ACTUALLY mean in the ETSI standard?

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u/Accomplished-Stay441 — 2 days ago
▲ 1 r/PCB+1 crossposts

https://preview.redd.it/es052q96n9zg1.png?width=950&format=png&auto=webp&s=69fff2b6d6c76bf87fea6a7ca126d40fa95e2d54

https://preview.redd.it/jrhwnk77n9zg1.png?width=950&format=png&auto=webp&s=b8f0a5bd06c6814a016a7315d65ffb9518031a97

https://preview.redd.it/tieid5k8n9zg1.png?width=950&format=png&auto=webp&s=2271bc0a69efed6af221c80c9ef5644883a2a825

https://preview.redd.it/4daro6xan9zg1.png?width=769&format=png&auto=webp&s=f9f67ffcee9fcebffc8e0581b62e96aec5c71333

https://preview.redd.it/48f4oxddn9zg1.png?width=704&format=png&auto=webp&s=62a919b241d401c9247601ffdb90772951012606

https://preview.redd.it/ibnny76ln9zg1.png?width=1393&format=png&auto=webp&s=3b23cd43ea3cfab7e954fc639876dfeed35afe69

So its basically to built an transmitter circuit...I took schematic of 433MHz FS1000A circuit and integrated it with the PCB..I have consider the component placements and no ground plane near 22mm near of antennae and some other facts...But knowing more I feel I have done many things wrong..I couldnt find anything that would test my design...Also felt it would be great to hear from experts than some AI powered sites....This is my first PCB so pls consider it while reviewing it 😞...Pls feel free to ask for further question on my objectives and designs if I wasnt well enough to convey you all with this description.

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u/Accomplished-Stay441 — 9 days ago